Thermal Via Array Resistance

Formula

Description

Thermal vias are plated through-holes placed under a heat-generating component to conduct heat from the top copper layer to a large ground plane on an inner or bottom layer. Vias in parallel reduce the total thermal resistance by a factor of n. A typical 0.3 mm diameter plated via with 25 µm copper plating through a 1.6 mm board has a thermal resistance of about 70-100°C/W. An array of 20 such vias reduces this to about 3.5-5°C/W, making it practical for thermal management of QFN and BGA packages with exposed thermal pads.

Variables

• R_array — Combined thermal resistance of the via array (°C/W)
• R_single — Thermal resistance of one via (°C/W)
• n — Number of vias in the array

Practical Notes

Via thermal resistance depends on diameter, plating thickness, and board thickness. Filled and capped vias (via-in-pad) have lower thermal resistance than open vias. Via-in-pad requires VIPPO (Via In Pad Plated Over) process to prevent solder wicking during assembly. For best thermal performance, place vias on a regular grid with 1-1.2 mm pitch directly under the thermal pad. Solder-filled vias have significantly lower thermal resistance than air-filled ones.