PCB Trace Signal Delay

Formula

Description

The signal delay through a PCB trace is simply the trace length divided by the propagation velocity. This is critical for high-speed digital design where signals on different nets must arrive at the receiver within a specified time window (setup and hold times). Length matching ensures that parallel data bus signals and their clock arrive simultaneously. For DDR memory interfaces, differential pairs, and LVDS links, delay matching to within 5-25 ps (1-5 mm) is commonly required.

Variables

• td — Signal propagation delay (s)
• length — Physical trace length (m)
• v_p — Propagation velocity (m/s)

Practical Notes

For FR-4 microstrip, the delay is approximately 6.0-6.3 ps/mm (150-160 ps/inch). For FR-4 stripline, the delay is approximately 6.8-7.1 ps/mm (170-180 ps/inch). A 100 mm microstrip trace has about 600 ps delay. For a 1 GHz clock (1 ns period), this is 60% of one clock period, which is very significant. Trace delay must be accounted for in timing budgets for any interface faster than about 50 MHz.