Delay-Matched Trace Length

Formula

Description

Length matching converts a timing skew requirement into a maximum allowed trace length difference. For parallel buses (DDR, LVDS, parallel ADC interfaces), all data signals must arrive at the receiver within the setup/hold time window relative to the clock. The maximum allowable skew Δt translates to a physical length tolerance Δl based on the propagation velocity. Serpentine (meandering) routing is used to add length to shorter traces, equalizing the delay across all signals in a bus.

Variables

• Δl — Maximum trace length difference (m)
• v_p — Propagation velocity (m/s)
• Δt — Maximum allowable timing skew (s)

Practical Notes

For FR-4 microstrip (vp ≈ 165 mm/ns): 1 ps skew = 0.165 mm length. DDR4 requires data-to-strobe matching within about ±5 mm. USB 3.0 differential pair intra-pair skew must be < 5 mils (0.127 mm). HDMI skew requirement is ±2 mm within a pair and ±5 mm between pairs. When routing serpentine patterns, use smooth curves (not sharp corners) to minimize impedance discontinuities and crosstalk.