Jitter from Phase Noise

Formula

Description

Phase noise on a clock or oscillator signal translates directly to timing jitter. The integrated phase noise power over the bandwidth of interest determines the RMS jitter. Higher carrier frequencies have less jitter for the same phase noise because each radian of phase error represents a smaller fraction of the period. This relationship is critical for high-speed serial links (PCIe, USB, HDMI), ADC sampling clocks, and communication systems where jitter directly impacts bit error rate. Phase noise is typically integrated from 12 kHz to 20 MHz for serial link analysis.

Variables

• Tj — RMS timing jitter (s)
• ∫L(f)df — Integrated SSB phase noise power (rad² rms)
• f0 — Carrier (clock) frequency (Hz)

Practical Notes

For a 100 MHz clock with -100 dBc/Hz phase noise flat from 10 kHz to 10 MHz: integrated noise = 10⁻¹⁰ × 10⁷ = 10⁻³ rad², Tj ≈ 71 ps rms. PCIe Gen3 requires <1.5 ps rms jitter on the reference clock. DDR4 requires <3 ps rms. Low-jitter clock generators use crystal oscillators with PLL multiplication rather than RC oscillators.