PLL Output Frequency

Formula

Description

A phase-locked loop (PLL) generates an output frequency that is a rational multiple of the reference frequency. The reference divider R divides the reference clock down to the phase detector comparison frequency (f_ref/R), and the feedback divider N divides the VCO output to the same frequency. In lock, f_out/N = f_ref/R, giving f_out = f_ref × N/R. By choosing N and R, almost any output frequency can be synthesized from a single reference crystal. PLLs are used in clock generators, frequency synthesizers, and clock recovery circuits.

Variables

• f_out — PLL output frequency (Hz)
• f_ref — Reference oscillator frequency (Hz)
• N — Feedback divider ratio (integer)
• R — Reference divider ratio (integer)

Practical Notes

The phase detector comparison frequency (f_ref/R = f_out/N) determines the PLL loop bandwidth limit and the channel spacing in frequency synthesizers. Higher comparison frequency allows faster lock time and lower phase noise, but requires larger N for the same output frequency. Fractional-N PLLs allow non-integer N values using delta-sigma modulation, enabling finer frequency resolution without reducing the comparison frequency.