PWM Resolution (Bits)

Formula

Description

The resolution of a timer-based PWM output is determined by the ratio of the timer clock frequency to the desired PWM frequency. The timer counts from 0 to (fclk/fpwm − 1), giving fclk/fpwm distinct duty cycle steps. The resolution in bits is the base-2 logarithm of this count. Higher timer clock frequencies or lower PWM frequencies give more resolution. For example, a 72 MHz timer generating a 20 kHz PWM has 72M/20k = 3600 steps ≈ 11.8 bits of resolution.

Variables

• bits — PWM duty cycle resolution in bits
• f_clk — Timer clock frequency (Hz)
• f_PWM — PWM output frequency (Hz)

Practical Notes

Common applications: LED dimming requires 10-12 bits for smooth visual perception. Motor control typically needs 8-12 bits. Audio-class PWM (class D amplifiers) requires 12-16 bits. If the calculated resolution is insufficient, options include: increasing the timer clock, decreasing the PWM frequency, or using dithering to achieve fractional bit resolution. Some microcontrollers offer high-resolution PWM timers (e.g., STM32 HRTIM at 4.6 GHz equivalent) for precisely controlled duty cycles.