Clock Skew Timing Margin

Formula

Description

Clock skew is the difference in clock arrival times at two different flip-flops due to different clock distribution path lengths. When data must travel from one flip-flop to another, the clock skew effectively reduces the available time for data propagation. Positive skew (clock arrives later at the destination) steals from the setup time budget, while negative skew adds to it. In board-level design with multiple ICs sharing a clock, trace length differences create skew that must be accounted for in the timing budget.

Variables

• Tmargin — Available timing slack (s)
• Tclk — Clock period (s)
• Tskew — Clock skew between source and destination (s)
• Tsetup — Setup time requirement of the destination flip-flop (s)

Practical Notes

Clock distribution techniques to minimize skew: clock trees (H-tree), clock buffers (zero-delay buffers like CY2305), and source-synchronous clocking (sending the clock alongside data). DDR memory uses source-synchronous DQS strobes to eliminate clock skew. For PCB-level clock distribution, match trace lengths to within 1-2mm for clock rates above 100 MHz.