CMOS Dynamic Power

Formula

Description

CMOS dynamic power dissipation occurs when gates switch states, charging and discharging their load capacitances. The quadratic voltage dependence is why modern processors aggressively reduce supply voltage to save power. The capacitance term includes gate input capacitance, interconnect capacitance, and any external load. Reducing clock frequency linearly reduces dynamic power, which is the basis for dynamic frequency scaling in modern processors. This is the dominant power component in active CMOS circuits.

Variables

• P — Dynamic power dissipation (W)
• C — Total switched capacitance (F)
• V — Supply voltage (V)
• f — Switching frequency (Hz)

Practical Notes

Total CMOS power also includes static (leakage) power and short-circuit power. At advanced process nodes (below 28nm), leakage power becomes comparable to dynamic power. Activity factor (α) is often included: P = α × C × V² × f, where α is the fraction of gates switching per cycle (typically 0.1-0.3).