Static Power Dissipation

Formula

Description

Static power dissipation in CMOS circuits is caused by leakage currents that flow even when transistors are not switching. Sub-threshold leakage increases exponentially as threshold voltages are reduced in advanced process nodes. Gate oxide tunneling current also contributes in very thin oxide processes. For modern processors at 7nm and below, static power can account for 30-50% of total power consumption. Low-power designs use power gating, multi-threshold transistors, and body biasing to manage leakage.

Variables

• P — Static power dissipation (W)
• Vdd — Supply voltage (V)
• Ileakage — Total leakage current (A)

Practical Notes

Leakage current roughly doubles for every 10°C increase in temperature, creating a thermal runaway risk if not managed. Sleep and deep-sleep modes in microcontrollers reduce leakage by powering down unused sections. Typical MCU sleep currents range from nanoamps to microamps depending on what peripherals remain active.