Logic Noise Margin

Formula

Description

The noise margin is the maximum amount of noise voltage that can be added to a digital signal without causing a logic error at the receiving gate. The high-state noise margin (NMH) is the difference between the minimum output high voltage (VOH) and the minimum input high voltage threshold (VIH). Similarly, the low-state noise margin (NML) = VIL − VOL. Adequate noise margins are essential for reliable digital communication over PCB traces, cables, and backplanes. When noise margins are insufficient, data errors, glitches, and metastability can occur.

Variables

• NM — Noise margin voltage (V)
• V_OH — Minimum output high voltage (V)
• V_IH — Minimum input high voltage threshold (V)

Practical Notes

Typical noise margins: TTL 0.4 V (both NMH and NML), CMOS at 3.3 V about 1.0 V, LVDS 0.1 V (but differential, so effective margin is better). Higher supply voltage generally provides more noise margin. Level translation is required when interfacing logic families with different voltage levels. For long traces, use differential signaling (LVDS, RS-485) which provides much better noise immunity than single-ended logic.