Digital Fanout

Formula

Description

Fanout is the maximum number of gate inputs that a single output can drive while maintaining valid logic levels. The driving gate must source (or sink) enough current to satisfy all connected inputs. For static CMOS, input currents are negligible (nanoamps of leakage), so fanout is essentially unlimited by DC current. However, dynamic fanout is limited by the capacitive loading of each input (typically 2-10 pF), which slows down signal edges and increases propagation delay. For TTL and BiCMOS, both static current and capacitive loading must be considered.

Variables

• N — Maximum number of gates that can be driven
• I_source — Maximum current the driver can source/sink (A)
• I_sink — Input current required by each receiving gate (A)

Practical Notes

Standard TTL fanout is 10 (IOH = 0.4 mA, IIH = 40 µA). CMOS fanout is theoretically unlimited by DC current but practically limited by capacitive loading to about 20-50 gates before timing degradation becomes unacceptable. For high-fanout nets (clocks, resets), use buffer trees or dedicated clock distribution ICs. In FPGA designs, high fanout nets are automatically handled by the place-and-route tool using buffer insertion.